The present invention relates to an insulated gate field effect transistor (IGFET), particularly to an IGFET which has been subjected to the selective oxidation process with the silicon nitride film (Si.sub.3 N.sub.4 film) used as the maks.
The IGFET which has been subjected to the selective oxidation process using the Si.sub.3 N.sub.4 film as the mask shows less parastic channel effect since the silicon dioxide film (SiO.sub.2 film) on the area other than the gate is sufficiently thick. On the other hand, when it is adopted especially to an integrated circuit (IC), it provides excellent effects such as the integration density can be much improved and occurrence of disconnection in wiring is reduced. However, simultaneously, the selective oxidation process brings about possibility of dielectric break down of the insulated gate film at a low voltage when the electric field is applied to the substrate from the gate electrode via the insulated gate film. Namely, such IGFET has a problem that the break down voltage of the insulated gate film is lowered by the abovementioned selective oxidation process.
FIG. 1 to FIG. 4 show formation of field oxidized film by the selective oxidation in the ordinary IGFET and the causes of lowered break down voltage of the insulated gate film which are currently considered.
At first, as indicated in FIG. 1, the silicon dioxide film 2 (SiO.sub.2 film) is formed in the thickness of about 500 .ANG. on the entire surface of single crystal silicon substrate 1, and then the silicon nitride film (Si.sub.3 N.sub.4 film) 3 is selectively formed in the similar thickness on said SiO.sub.2 film 2. Next, as indicated in FIG. 2a, the field oxide film 22 is caused to grow up to the thickness of about 8000 .ANG. on the single crystal silicon substrate 1 except for the gate under a high temperature oxidizing atomosphere containing water vapor. However, in this selective oxidation proces, H.sub.2 O in the water vapor and the Si.sub.3 N.sub.4 film 3 react chemically as expressed by the reaction (1), producing NH.sub.3. EQU Si.sub.3 N.sub.4 +6H.sub.2 O=4NH.sub.3 +3SiO.sub.2 . . . (1)
The ammonia (NH.sub.3) easily passes through the SiO.sub.2 film and therefore the NH.sub.3 generated by the reaction (1) reaches the area under the SiO.sub.2 film 2 of the gate portion and then reacts with the single crystal silicon substrate 1 in accordance with the reaction (2), producing Si.sub.3 N.sub.4 21, 23. EQU 3Si+4NH.sub.3 =Si.sub.3 N.sub.4 +6H.sub.2 . . . (2)
Among the Si.sub.3 N.sub.4 21, 23 newly produced by the reaction (2), the Si.sub.3 N.sub.4 21 at the boundary of the single crystal silicon substrate 1 under the end of the oxidation resistant mask Si.sub.3 N.sub.4 3 is called the "White Ribbon". As indicated in FIG. 2b which shows an enlarged view of a part of FIG. 2a, this Si.sub.3 N.sub.4 21 is generated by the seepage of H.sub.2 O from the end of thick SiO.sub.2 film. Detail explanation is omitted here since it is explained by E. Kooi et al. in the Journal of Electro-Chemical Society Vol. 123, P117 (1976). In addition it is also explained by Kowada et al. in the Journal of Japanese Applied Physics Vol. 17, No. 4, P737 (1978) that the break down voltage of the insulated gate film is not lowered only by the Si.sub.3 N.sub.4 21 at the gate end region, the Si.sub.3 N.sub.4 has a possibility of existing in the gate center region. The reason is considered as follow, namely the NH.sub.3 generated by the reaction between H.sub.2 O and Si.sub.3 N.sub.4 because of the crystal defect such as a pin-hole in the Si.sub.3 N.sub.4 film 3 further reaches the Si substrate passing through the lower SiO.sub.2 film 2, producing Si.sub.3 N.sub.4 23. In addition, as indicated in FIG. 3, in the ordinary IGFET, the Si.sub.3 N.sub.4 film 3 and SiO.sub.2 film 2 are peeled after the selective oxidation, but the Si.sub.3 N.sub.4 21, 23 formed after the selective oxidation remains. This is mainly because the Si.sub.3 N.sub.4 21, 23 may not exist as the pure films but they may be complicatedly combined with the impurity particles being contained in the area near the surface of the single crystal silicon substrate 1 as the nuclei. Namely, since the insulated gate film is formed while these nitrides are remaining, a homogeneous film thickness cannot be obtained and resultingly the break down voltage is lowered. In the case of ordinary IGFET, the SiO.sub.2 to be provided between the gate electrode and the silicon base plate must be formed as thin as possible in order to make large the electrostatic capacitance at the gate portion. However, when the SiO.sub.2 film becomes thinner, the break down voltage is drastically lowered. Lowering of such break down voltage is a large barrier for improvement in the characteristics of the IGFET.
The method of lowering the reaction temperature at the time of selective oxidation is proposed by B. W. Ormont et al. in the Electro-Chemical Society Spring Meeting (Boston) Abstract No. 89 P231 (1979) as the means for solving such lowering of the break down voltage in the insulated gate film due to the selective oxidation.
However, a method of lowering the reaction temperature is inadequate for the actual process because the oxidation time of about 5 hours is usually required for obtaining the field oxide film of about 8000 .ANG. under a temperature of 1100.degree. C. but about 13 to 14 hours are required under a temperature of 950.degree. C. Moreover, B. W. Ormont et al. also propose a method of using a thick Si.sub.3 N.sub.4 film as the oxidation resistant mask. But, it is still undesirable measure to make thick the Si.sub.3 N.sub.4 film enough for preventing lowering of the break down voltage because a stress applied on the base plate at the time of selective oxidation increases.
Therefore, expected is appearing of such an IGFET as not allowing lowering of the break down voltage of the gate insulating film even when the selective oxidation is perpormed using the Si.sub.3 N.sub.4 film as the mask.